Threshold voltage instabilities in M.O.S. silicon-gate transistors.

Because of the large number of elements integrated, on complex MOS LSI circuits, the evaluation of their reliability at the component level is difficult to assess, hence alternate methods are needed. One method used by manufacturers, is to fabricate test patterns on the MOS LSI slice and to use these test patterns to evaluate and control the reliability of the process and circuits. The stability of MOS devices is largely dependent on the quality of the gate oxide and on the quality of the oxide-silicon interface. Bias-temperature testing can be performed on MOS test transistors to accelerate threshold voltage drift. Observing the direction of this drift,  calculating the activation energy of the drift mechanism and evaluating the magnitude of the drift with respect to time and temperature, the reliability of the process and LSI device can be assessed and the cause of the drift determined. Studies performed on test transistors manufactured on Microsystems International p-and n-channel MOS silicon-gate processes show that little or no contamination was present in the gate oxide and that the drift was caused by slow-trapping of charges in the oxide-silicon interface. The activation energy of the trapping mechanism was 1.18eV for p-channel. N-channel transistors showed stabilities better than p-channel. The threshold voltage drift observed on both p- and n-channel transistors will not affect the long term reliability of circuits operating over normal temperature ranges.