A High Resolution of MCML-Based Time-to-Digital Converter Implementation

A new high-resolution time-to-digital converter (TDC) architecture based on MOS Current-Mode-Logic (MCML) was described. Aiming at high resolution and large dynamic range, the prototype was designed using Virtuoso Cadence Analog Design Environment (ADE) and implemented with 0.13 µm CMOS technology. A minimum time domain resolution of 8.24 pS and a dynamic range of 9 bits were achieved. The capability of operating with variable resolutions was described. With the novel multi-step switchable configuration, the TDC is able to operate with four specific resolutions which are 8.24 pS, 10.83 pS, 12.98 pS and 14.3 pS. Each operation mode corresponds to a different power consumption, which makes the new TDC architecture suitable for being embedded in various systems. For instance, a LIDAR is one of the feasible applications. The design and implementation were verified through simulation results.