High Speed Low Error Floor Hardware Implementation and Fast and Accurate Error Floor Estimation of LDPC Decoders

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Tolouei, Sina




This thesis explores hardware implementation of low error floor and high speed low-density parity-check (LDPC) decoders.
At first, a novel partially-parallel implementation of a protograph-based quasi-cyclic (QC) LDPC decoder, using a new column-layered message-passing schedule is presented.
A new design for serial-input check nodes and switch networks, results in lower hardware complexity while having a higher throughput and comparable latency in comparison with all existing partially-parallel architectures.

Thereafter, we introduce a multi-step scheme for the input quantization of
message-passing decoders for LDPC codes.
The scheme is based on successive re-quantization and re-decoding of the input blocks that cause the decoder to be trapped in a trapping set, until the decoding is successful or a maximum number of re-quantization/re-decodings is reached.
The proposed scheme, which is applicable to both regular and irregular codes, lowers the error floor significantly at the cost of small increase in complexity, memory and latency.

Furthermore, to facilitate the process of code design and performance evaluation in the error floor region, we design a fast and
accurate technique to estimate the error floor of variable-regular LDPC codes under quantized iterative decoding algorithms.
This technique, which is based on enumerating the dominant elementary trapping sets of the code, provides significant improvement over existing methods in terms of speed and accuracy.

Finally, we examine the harmfulness of trapping sets of variable-regular LDPC codes for soft-decision iterative decoding algorithms.
We show that, other than the size of a trapping set, the number of unsatisfied check nodes and the trapping set's topological properties, the
position of its subgraph in the Tanner graph of the code can also have an effect on its harmfulness.
We also examine dominant trapping sets of the quantized min-sum (MS) decoding algorithm and two of its variants (offset-MS and MS with successive relaxation (SR)), for both regular and irregular LDPC codes.
We show that the distribution of dominant trapping sets of these algorithms is similar for regular codes and different for irregular codes.
Based on these results, we evaluate the error floor performance of a decoder, consisting of MS, offset-MS and SR-MS decoding algorithms working in


Engineering - Electronics and Electrical




Carleton University

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Engineering, Electrical and Computer

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Theses and Dissertations

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