This thesis presents the design and implementation of an All-Digital Phase Locked Loop (ADPLL) that uses Delta-Sigma (ΔΣ) modulation, multi-phase outputs, and Dynamic Element Matching (DEM). The system is designed using a combination of 65nm CMOS technology and an FPGA. The frequency range of the ADPLL output is 5.48GHz to 6.22GHz. Several design techniques are used to reduce the phase noise of the ADPLL output. The ADPLL uses a rotary travelling wave-based Digitally Controlled Oscillator (DCO) with multi-phase outputs to improve quantization noise. Manufacturing variations on the fine-tuning DCO input capacitors are averaged using DEM to produce more uniform frequency steps. ΔΣ modulation is used on the least significant of the DCO input bits. This modulation introduces a dithering effect on the output frequency that has the effect of moving some of the phase noise away from the ADPLL carrier frequency.