A Rotary Travelling Wave Oscillator Based All-Digital PLL in 65nm CMOS
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This thesis presents the design and implementation of an All-Digital Phase Locked Loop (ADPLL) that uses Delta-Sigma (ΔΣ) modulation, multi-phase outputs, and Dynamic Element Matching (DEM). The system is designed using a combination of 65nm CMOS technology and an FPGA. The frequency range of the ADPLL output is 5.48GHz to 6.22GHz. Several design techniques are used to reduce the phase noise of the ADPLL output. The ADPLL uses a rotary travelling wave-based Digitally Controlled Oscillator (DCO) with multi-phase outputs to improve quantization noise. Manufacturing variations on the fine-tuning DCO input capacitors are averaged using DEM to produce more uniform frequency steps. ΔΣ modulation is used on the least significant of the DCO input bits. This modulation introduces a dithering effect on the output frequency that has the effect of moving some of the phase noise away from the ADPLL carrier frequency.
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Copyright © 2017 the author(s). Theses may be used for non-commercial research, educational, or related academic purposes only. Such uses include personal study, research, scholarship, and teaching. Theses may only be shared by linking to Carleton University Institutional Repository and no part may be used without proper attribution to the author. No part may be used for commercial purposes directly or indirectly via a for-profit platform; no adaptation or derivative works are permitted without consent from the copyright owner.
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cathcart-arotarytravellingwaveoscillatorbasedalldigital.pdf | 2023-05-05 | Public | Download |