Reduced Capacitor Eight Bit SAR Analog to Digital Converter

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Creator: 

Lanfranconi, Daniel James

Date: 

2014

Abstract: 

The charge sharing SAR ADC is a hybrid between the binary weighted SAR ADC and
the serial SAR ADC.The charge sharing SAR ADC has less capacitors, and therefore
less die area and less leakage than a binary weighted SAR ADC. It’s conversion time is
less than the serial SAR ADC because it uses a capacitor array with more capacitors
than the serial SAR ADC.

The simulated signal to noise ratio (SNR) was measured to be 49.9dB. The simulated signal to noise and distortion ratio (SINAD) was measured to be 48.72dB. The simulated effective number
of bits (ENOB) was measured to be 7.8bits.
The simulated total harmonic distortion
(THD) was measured to be -60.3dB. The simulated spurious free dynamic range (SFDR)
was measured to be 60.4dB. The simulated worst case dynamic nonlinearity, differential
non-linearity (DNL) and integral non-linearity (INL) are less than 1/2 least significant
bit (LSB).

Subject: 

PHYSICAL SCIENCES Engineering - Electronics and Electrical

Language: 

English

Publisher: 

Carleton University

Thesis Degree Name: 

Master of Applied Science: 
M.App.Sc.

Thesis Degree Level: 

Master's

Thesis Degree Discipline: 

Electrical and Computer Engineering

Parent Collection: 

Theses and Dissertations

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