Iterative decoding in analog VLSI

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Creator: 

Hemati, Saied

Date: 

2005

Abstract: 

This thesis explores theoretical and practical aspects of iterative decoding algorithms when they are implemented on analog continuous-time platforms. Analog continuous-time iterative decoding was proposed a few years ago to improve the power/speed ratio of decoder chips that decode capacity achieving codes. It was commonly believed that replacing discrete-time processing modules with analog circuits would not change the dynamics of the iterative decoder. On the contrary, we show that not only does continuous-time iterative decoding have different dynamics, but also its error correcting performance can surpass that of conventional iterative decoders. We also present a simple model for ideal continuous-time iterative decoding.

As a direct consequence of our study on the dynamics of analog decoders, we show that by looking at the decoding as a numerical problem and using advanced numerical techniques, we are able to improve the convergence rate and decoding performance of iterative decoding algorithms.

Furthermore, we devise novel processing modules for implementing affordable high-speed analog min-sum iterative decoders by using strongly inverted CMOS transistors. This is favorable because previously reported analog decoders were either BiCMOS or weakly inverted CMOS designs. The former could be fast but is rather expensive and the latter would be low-power but it is not fast enough for many applications. Our design is modular and the main blocks are constructed based on current mirrors and virtually any accurate current mirror can be used as the main block in our design. As an example, we show how the building modules can be designed in deep submicron CMOS technologies. We also present an appropriate design methodology for implementing high-degree blocks that can drastically reduce silicon area and power consumption.

To prove the functionality of the proposed circuits, an analog min-sum iterative decoder chip for a (32,8) regular LDPC code was designed and fabricated in 0.18pm CMOS technology. This chip is the first analog min-sum iterative decoder. Also, it is the first functional analog iterative decoder for an LDPC code and is the fastest reported analog CMOS iterative decoder. Measurement results not only show that the proposed circuits are functional but also confirm the validity of our proposed model for ideal analog decoding. In fact, when noise in the channel is dominant compared to the imperfections in the analog iterative decoder, the simulation results based on our proposed model are close to the measurement results.

Subject: 

Coding theory.
Iterative methods (Mathematics)
Integrated circuits -- Very large scale integration.
Error-correcting codes (Information theory)
Metal oxide semiconductor field-effect transistors.
Algorithms.

Language: 

English

Publisher: 

Carleton University

Thesis Degree Name: 

Doctor of Philosophy: 
Ph.D.

Thesis Degree Level: 

Doctoral

Thesis Degree Discipline: 

Engineering, Electrical

Parent Collection: 

Theses and Dissertations

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