Advanced Framework for Transient Simulation of High-Speed Circuits and Interconnects Using L-Stable High-Order Integration Methods

The trends toward higher operating frequencies and sharper rise times \hla{coupled} with faster switching signals have made modeling and simulation of high-speed interconnects an increasingly challenging task. Typically, the circuit models arising from characterizing coupled high-speed interconnects are very large linear circuits with many linear components, making the transient analysis a cumbersome task. Recently, waveform relaxation methods based on transverse partitioning (WR-TP) were proposed to address this issue. It was shown that the complexity of WR-TP grows only linearly with the number of lines. However, as the coupling between the lines becomes stronger, the WR-TP algorithm either fails to converge or the number of iterations required for convergence increases. To address the issue of convergence in WR-TP, an overlapping partitioning (OP) method is presented in this thesis proposal. Using the OP approach, the coupled interconnects are partitioned such that each subcircuit contains one or more lines that are tightly coupled, while allowing the lines between adjacent subcircuits to overlap. The weak coupling between the subcircuits are represented using voltage/current sources. Next, each subcircuit is simulated independently using a suitable integration method for the whole time of interest. The voltage/current sources representing the coupling between the subcircuits are then updated. This process is repeated until convergence is obtained. Typically, during the simulation of each subcircuit, an integration method is used to discretize the time points by taking finite time steps to approximate the waveforms at those time points. Recently, it has been shown that using a high-order and $L$-stable integration methods based on Obreshkov formula (ObF) can lead to a large reduction in the transient analysis time of general circuits. In this thesis, we show that by using ObF and taking advantage of the special structure of the mathematical formulation of the interconnect circuits, the simulation time of each subcircuit can be significantly reduced. Thus, reducing the overall simulation time.