Reducing clock power in synchronous circuit design.

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Creator: 

Zhang, Yi

Date: 

1998

Subject: 

Asynchronous Circuits -- Design And Construction
Metal Oxide Semiconductors, Complementary -- Design And Construction
Integrated Circuits -- Very Large Scale Integration -- Design And Construction
Low Voltage Integrated Circuits -- Design And Construction

Language: 

English

Publisher: 

Carleton University

Thesis Degree Name: 

Master of Engineering: 
M.Eng.

Thesis Degree Level: 

Master's

Thesis Degree Discipline: 

Engineering, Electrical

Parent Collection: 

Theses and Dissertations

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