A Phased-Scaled Vernier Time-to-Digital Converter Architecture with Switchable Coarse/Fine Resolutions, Wide Range and Ultra Low Power Consumption

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Creator: 

Wang, Tuoxin

Date: 

2016

Abstract: 

A novel phase-scaled Vernier time-to-digital converter (TDC) architecture with a switchable coarse/fine (16ps/2ps) time resolution function is presented to achieve large phase (time) detection range (32.7ns in 14 bits), fine time resolution (2ps), compact size and super low power consumption simultaneously. The phase noise (caused by the TDC) can also be improved due to it allowing a higher reference frequency compared to other types of TDC architectures.

Subject: 

Engineering - Electronics and Electrical

Language: 

English

Publisher: 

Carleton University

Thesis Degree Name: 

Master of Applied Science: 
M.App.Sc.

Thesis Degree Level: 

Master's

Thesis Degree Discipline: 

Engineering, Electrical and Computer

Parent Collection: 

Theses and Dissertations

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