A Phased-Scaled Vernier Time-to-Digital Converter Architecture with Switchable Coarse/Fine Resolutions, Wide Range and Ultra Low Power Consumption
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A novel phase-scaled Vernier time-to-digital converter (TDC) architecture with a switchable coarse/fine (16ps/2ps) time resolution function is presented to achieve large phase (time) detection range (32.7ns in 14 bits), fine time resolution (2ps), compact size and super low power consumption simultaneously. The phase noise (caused by the TDC) can also be improved due to it allowing a higher reference frequency compared to other types of TDC architectures.
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Copyright © 2016 the author(s). Theses may be used for non-commercial research, educational, or related academic purposes only. Such uses include personal study, research, scholarship, and teaching. Theses may only be shared by linking to Carleton University Institutional Repository and no part may be used without proper attribution to the author. No part may be used for commercial purposes directly or indirectly via a for-profit platform; no adaptation or derivative works are permitted without consent from the copyright owner.
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- 2016
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wang-aphasedscaledverniertimetodigitalconverter.pdf | 2023-05-04 | Public | Download |