The purpose of this thesis was to study the insight of the time-to-digital converter (TDC) technology which is expected to be employed in an all-digital phase-locked loop (ADPLL) frequency (clock) synthesizer application in order to reduce its phase noise (jitter). A novel ring-type TDC architecture and design have been proposed for achieving competitive performances in contrast to the current state-of-the-art literature. A phenomenon called parallel-output misalignment (POM), which intrinsically occurs in every ring-type TDCs like gated ring oscillator (GRO) or Vernier-ring TDCs is analyzed comprehensively. We found that the phase noise caused by POM error may be larger than that due to quantization error (from time resolution characteristic) by up to 22dB or even more. Consequently, the overall phase noise contribution might be dominated by the POM effect rather than the quantization error. This paper proposes a (tunable) conjoined-ring Vernier (CRV) TDC with a POM error correction circuit that can eliminate the POM error and its consequent corruption on phase noise performance, making quantization error being the only contribution of the overall phase noise. Meanwhile, the proposed TDC implementation may maintain competitive performance in terms of fine time resolution (0.8ps) and a flexible large time residual detection range in a 40nm CMOS technology. In addition, a configurable digital control that enables a tuning time resolution (0.8ps~1.1ps) function and achieves a superior sub-pico-second performance has been built up. A freely switchable coarse/fine resolution scheme has been realized so as to achieve the best figure of merit considering both resolution performance and power consumption. The proposed Partial Conjoined-Ring Vernier TDC design and the corresponding circuit have been approved and issued by US Patent Office in 2018.