Power and Area Efficient Sub-threshold 6T SRAM with Horizontal Local Bit-Lines and Bit-Interleaving

It appears your Web browser is not configured to display PDF files. Download adobe Acrobat or click here to download the PDF file.

Click here to download the PDF file.

Creator: 

Basuta, Sukneet

Date: 

2015

Abstract: 

SRAM in the typical microprocessor consumes a substantial amount of on-chip area and significantly contributes to static power dissipation. This study presents a new SRAM architecture with minimum area that utilizes a modified 6T SRAM cell for sub- and near-threshold operation in ultra-low power applications. This new architecture introduces horizontal bit-lines, mitigates half-select disturb, and supports bit-interleaving. The proposed design's stability was thoroughly tested in the presence of process, temperature, and voltage variations and compared to the standard 6T and traditional
8T cells. A 32kb SRAM block implementing the proposed architecture was designed, simulated, and compared to a traditional 8T SRAM cell block. The results show that the proposed design has lower power consumption than the 8T SRAM block, comparable read performance, and better write performance. This was all achieved while only having a 10\% increase in area per bit over the conventional 6T thin-cell layout.

Subject: 

Engineering - Electronics and Electrical

Language: 

English

Publisher: 

Carleton University

Thesis Degree Name: 

Master of Applied Science: 
M.App.Sc.

Thesis Degree Level: 

Master's

Thesis Degree Discipline: 

Engineering, Electrical and Computer

Parent Collection: 

Theses and Dissertations

Items in CURVE are protected by copyright, with all rights reserved, unless otherwise indicated. They are made available with permission from the author(s).