Gate-Oxide-Short Defect Analysis and Fault Modeling Based on FinFET's 3D Structure

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Dibaj, Roya




FinFET is one of the most promising candidates in replacing planar MOSFET beyond the 22nm technology node due to further improvements in the transistor performance. However, the complexity of FinFET manufacturing process due to its three-dimensional structure and reduced critical dimensions have caused new challenges in achieving reliable device testing. With the emergence of new types of defects and dominance of others, accurate modeling of the defects and generation of reliable fault models are essential to create realistic set of test vectors to detect the defects.

Automatic test pattern generation (ATPG) algorithms use traditional fault models that primarily capture the behavior of the circuit-under-test by introducing defects at the primary inputs and outputs. It has been found that many defects escape testing when they occur within the circuit structure. Recently, Cell-Aware Test (CAT) has been proposed to detect cell-internal defects by performing extensive analog simulations on post-layout standard circuit structures to generate the fault models. Although CAT methodology has significantly improved the defect coverage of the generated test patterns in MOSFET-based circuits, the defect models utilized are obtained based on the defects injected at the layout level and primarily represented by fixed lumped passive components that cannot reflect the true defect nature in the complex 3D structure of FinFET. Gate-Oxide-Short (GOS) is one of the dominant defects, which has significant impact on circuit reliability. It is the most complex to analyze and difficult to accurately model true behavior of the defective device.

This thesis presents a novel methodology for GOS defect injection and fault modeling in FinFETs by introducing the defect to a 3D structure of the device for a specific process technology. The behavior of the defective device is captured through simulations in Sentaurus TCAD environment that lead to the generation of more accurate defect models. These defect models are used in circuit-level simulations to generate appropriate fault models for the circuit structures. These cell-aware models could be integrated in CAT environment to generate more realistic test patterns. This research will not only be used in test pattern generation, but it will aid in cell-aware diagnosis and yield analysis.


Engineering - Electronics and Electrical




Carleton University


Chia-Hong Jan

Thesis Degree Name: 

Doctor of Philosophy: 

Thesis Degree Level: 


Thesis Degree Discipline: 

Engineering, Electrical

Parent Collection: 

Theses and Dissertations

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