This thesis discusses the performance improvement frequency synthesizers, which are commonly used circuits found in many electronic systems with the focus on alleviating the detrimental effects that temperature drifts or supply voltage changes can have. Either could require the oscillator to switch frequency bands to maintain lock, which would result in cycle slipping and phase offsets. A solution is described, involving the modification of capacitor bank switching circuits to incorporate a sub-threshold switching to allow frequency band changes to occur slowly enough for the synthesizer feedback loop to track, thus preventing cycle slipping and phase offsets. This is demonstrated with a 0.009 to 1.4 GHz frequency synthesizer implemented in a 0.18 μm SiGe BiCMOS process and achieves 365 fs integrated jitter at 1.05 GHz with a total power consumption of 81 mW. Measurements of the band switching circuit shows it prevents cycle slipping during band switching and reduces the maximum frequency deviation by 99.3%. Measurements were conducted while changing the temperature and supply voltage, and a control voltage monitoring band switching circuit is shown which would be able to correctly switch bands as needed. The combination of these two allows a frequency synthesizer which has become resistant to transient phase effects resulting from temperature or supply voltage variations. Following this demonstration of the core slow switching concept, further circuit enhancements were developed, including the development of a programmable bias line, allowing for controllable rise/fall times of the band switching circuit and for compensation of process, voltage, and temperature variations through calibration. The rise and fall time of the slow switching circuit can be further increased by modulating the control signal with a pulse width modulated control signal. Finally, the susceptibility of the oscillator to power supply noise is also reduced through a change in resonator circuitry, eliminating a contributor of power supply noise up-conversion in complementary cross-coupled pair oscillators.