A configurable FPGA-based outlier detection hardware is presented. The FPGA implementation reduces the power consumption by 89% compared to the existing software implementations. The implemented outlier detection technique is based on the joint estimation of model parameters and outlier effects in time series. A configuration of our implementation is capable of detecting multiple additive outliers with a detection accuracy of 99% and has a false positive rate of 1.05%.

We used the MATLAB implementation of the technique to compare its accuracy to the implementation in "tsoutliers" package of R. Using the HDL Coder, we generated a configurable hardware implementation. The design is configurable by adjusting the number of iterations for the optimization process, the number of samples, and the critical value. A configuration of this design has a total power dissipation of 1.14W, while processing 35 million data points per second, giving an energy usage of 0.032 microjoule per processed data point.