Configurable FPGA-Based Outlier Detection for Time Series Data
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A configurable FPGA-based outlier detection hardware is presented. The FPGA implementation reduces the power consumption by 89% compared to the existing software implementations. The implemented outlier detection technique is based on the joint estimation of model parameters and outlier effects in time series. A configuration of our implementation is capable of detecting multiple additive outliers with a detection accuracy of 99% and has a false positive rate of 1.05%.We used the MATLAB implementation of the technique to compare its accuracy to the implementation in "tsoutliers" package of R. Using the HDL Coder, we generated a configurable hardware implementation. The design is configurable by adjusting the number of iterations for the optimization process, the number of samples, and the critical value. A configuration of this design has a total power dissipation of 1.14W, while processing 35 million data points per second, giving an energy usage of 0.032 microjoule per processed data point.
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Copyright © 2018 the author(s). Theses may be used for non-commercial research, educational, or related academic purposes only. Such uses include personal study, research, scholarship, and teaching. Theses may only be shared by linking to Carleton University Institutional Repository and no part may be used without proper attribution to the author. No part may be used for commercial purposes directly or indirectly via a for-profit platform; no adaptation or derivative works are permitted without consent from the copyright owner.
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vazhbakht-configurablefpgabasedoutlierdetectionfortime.pdf | 2023-05-05 | Public | Download |