Delay Asymmetry Correction Model for IEEE 1588 Synchronization Protocol

The thesis proposes a delay asymmetry correction (DAC) model to enhance the IEEE 1588 synchronization protocol. The purpose of this work is to mitigate the effects of unpredictable packet delay variations (PDV), which cause asymmetric link delays on timing packets, in order to improve the synchronization accuracy of the slave clock with respect to the master clock. This is done by computing the time difference between the master and the slave clock asymmetric communication link delays. The NS-2 results indicate that the proposed solution achieves high synchronization accuracy of the slave clock in the presence of various bi-directional traffic loads, network congestions, and temporary network outage. Furthermore, the solution also improves the slave accuracy when there is a routing path change due to the failure in the network. However, the proposed solution does not perform well when it is incorporated with the AOCM model.