Minimizing nMOS Edge Leakage in Fully Depleted Silicon-on-Insulator CMOS Using Poly-Buffered LOCOS Isolation

A process has been designed, implemented and tested to minimize edge-leakage effects in fully depleted silicon-on-insulator (FD SOI) nMOSFET (nMOS) devices encountered in previous student project SOI CMOS fabrication runs in the Carleton University Microfabrication Laboratory. A layout with test arrays, including enclosed geometry transistors, was designed to perform a test fabrication run. The process uses optimized oxidation steps and Poly-Buffered LOCal Oxidation of Silicon (PBL) isolation with minimal mask steps and fabrication time. The fabricated test transistors revealed that some subthreshold edge leakage was still present in the nMOS devices. SEM imaging showed that the field oxide had been almost entirely unintentionally etched away during processing. This reduction in the field oxide thickness creates parasitic edge transistors. Sentaurus simulations imply that if not for this field oxide loss, the fabricated nMOS devices would have had minimal leakage with no kink in the subthreshold curve.