Wireline transceivers are explored to understand their limitations and how performance can be pushed. This exploration leads to the revelation that charge-steering based transceivers have a high potential. An in-depth transient analysis of the basic charge-steering latch is presented, providing new insight into the operation of charge-steering circuits. This insight is utilized to develop design equations for the basic charge-steering latch. The design equations lead to improvement in charge-steering latch design of as much as 350%. Several new charge-steering latch topologies are also proposed. The transient analysis and design equations are extended to one of these latches. Post-layout simulations of these latches are done in 28nm FD-SOI CMOS and 65nm CMOS. The new design equations and latch topologies enable the use of charge-steering latches at 28Gb/s and beyond, at new levels of performance. Power savings of as much as 40% are demonstrated by the new topologies.