Charge-Steering Latches
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Wireline transceivers are explored to understand their limitations and how performance can be pushed. This exploration leads to the revelation that charge-steering based transceivers have a high potential. An in-depth transient analysis of the basic charge-steering latch is presented, providing new insight into the operation of charge-steering circuits. This insight is utilized to develop design equations for the basic charge-steering latch. The design equations lead to improvement in charge-steering latch design of as much as 350%. Several new charge-steering latch topologies are also proposed. The transient analysis and design equations are extended to one of these latches. Post-layout simulations of these latches are done in 28nm FD-SOI CMOS and 65nm CMOS. The new design equations and latch topologies enable the use of charge-steering latches at 28Gb/s and beyond, at new levels of performance. Power savings of as much as 40% are demonstrated by the new topologies.
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Copyright © 2018 the author(s). Theses may be used for non-commercial research, educational, or related academic purposes only. Such uses include personal study, research, scholarship, and teaching. Theses may only be shared by linking to Carleton University Institutional Repository and no part may be used without proper attribution to the author. No part may be used for commercial purposes directly or indirectly via a for-profit platform; no adaptation or derivative works are permitted without consent from the copyright owner.
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- 2018
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pike-chargesteeringlatches.pdf | 2023-05-05 | Public | Download |