A Message Passing Many-Core Architecture for an Asynchronous Graph Programming Model

Noticeable improvements in processor performance have been achieved by researching programming models, control flow parallelization, general architecture, memory access, and code compilation [53][4]. In this thesis, we seek to improve general processing by applying a many-core message passing (MPMC) architecture with a novel Asynchronous Graph Programming model (AGP). AGP abstracts higher-level languages into a graph of single instructions providing very high levels of parallelism and asynchronicity. The MPMC architecture utilizes a novel method of segmenting a graph among cores in tandem with the many-core model to exploit AGPs parallelism. We evaluate the MPMC architecture by implementing a functional simulation that, although incapable of providing empirical measurements, provides an an efficient method of evaluation that helps accelerate the development cycle. We found that the MPMC architecture can reach a 97% improvement in execution time from a single-core configuration, with room to improve given more cores and better node allocation strategies