Used in optical modems amongst a variety of other electronics applications, Integer-N PLL-based frequency synthesizers effectively multiply the frequency of a reference clock by an integer value to synthesize a higher frequency. When a synthesizer is packaged and its reference frequency should be generated externally, the solution is often to use another synthesizer system with another reference frequency and an oscillator that can tune to a valid reference frequency; one that divides evenly into the desired frequency. The proposed integrated-circuit solution divides a high-frequency clock already existing on the ASIC by a floating-point divisor to generate the packaged synthesizer's reference clock through the use of a sigma-delta divider and without requiring an additional oscillator. This thesis will detail the design considerations needed to allow tuning to a set of desired frequencies with a frequency error of less than 1 PPM and jitter less than 500 fs at the synthesizer output.