Fractional-N PLL-Based Frequency Synthesis Through Sigma-Delta Modulation of the Reference Clock Frequency

It appears your Web browser is not configured to display PDF files. Download adobe Acrobat or click here to download the PDF file.

Click here to download the PDF file.

Creator: 

Mikkelsen, Matthew Dillon

Date: 

2021

Abstract: 

Used in optical modems amongst a variety of other electronics applications, Integer-N PLL-based frequency synthesizers effectively multiply the frequency of a reference clock by an integer value to synthesize a higher frequency. When a synthesizer is packaged and its reference frequency should be generated externally, the solution is often to use another synthesizer system with another reference frequency and an oscillator that can tune to a valid reference frequency; one that divides evenly into the desired frequency. The proposed integrated-circuit solution divides a high-frequency clock already existing on the ASIC by a floating-point divisor to generate the packaged synthesizer's reference clock through the use of a sigma-delta divider and without requiring an additional oscillator. This thesis will detail the design considerations needed to allow tuning to a set of desired frequencies with a frequency error of less than 1 PPM and jitter less than 500 fs at the synthesizer output.

Subject: 

Engineering - Electronics and Electrical

Language: 

English

Publisher: 

Carleton University

Thesis Degree Name: 

Master of Applied Science: 
M.App.Sc.

Thesis Degree Level: 

Master's

Thesis Degree Discipline: 

Engineering, Electrical and Computer

Parent Collection: 

Theses and Dissertations

Items in CURVE are protected by copyright, with all rights reserved, unless otherwise indicated. They are made available with permission from the author(s).