Model-reduction techniques for high-speed interconnect analysis.

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Creator: 

Achar, Ramachandra

Date: 

1998

Subject: 

Computer-aided Design
Computer Algorithms
Integrated Circuits -- Very Large Scale Integration -- Design And Construction
Computer Architecture

Language: 

English

Publisher: 

Carleton University

Thesis Degree Name: 

Doctor of Philosophy: 
Ph.D.

Thesis Degree Level: 

Doctoral

Thesis Degree Discipline: 

Engineering, Electrical

Parent Collection: 

Theses and Dissertations

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