This research aims to increase the bandwidth of a transmission-line N-path filter around the clock frequency. The proposed filter consists of two four-path parallel stages with series inductors. The filter solves the trade-off between in-band insertion loss and out-of-band rejection of the original N-path filter. A high-frequency 4-phase non-overlapping clock generator with a 25% duty cycle is designed to drive the proposed filter. The proposed filter has a die area of 1.5 mm2 and was fabricated with CMOS 130-nm technology. The post-layout simulation results show that the filter is tunable from 0.1 to 1GHz, the bandwidth of 80 MHz can be achieved at 1 GHz and the noise figure of the filter is less than 3.2 dB over the frequency range. Unfortunately, the clock generator is not working properly,which is why measurement results show discrepancies from the simulated results. Several hypotheses are explored to explain the cause of these differences.