A diagonalization technique for the area reduction of programmable logic arrays.

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Creator: 

Harisha, Rajagopalan

Date: 

1983

Subject: 

Logic Circuits
Logic Design

Language: 

English

Publisher: 

Carleton University

Thesis Degree Name: 

Master of Engineering: 
M.Eng.

Thesis Degree Level: 

Master's

Thesis Degree Discipline: 

Engineering, Electrical

Parent Collection: 

Theses and Dissertations

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