This work demonstrates the development of a 5-bit time to digital converter (TDC) using the local passive interpolation (LPI) technique. The TDC architecture achieves a high resolution, while maintaining a low conversion latency, and a good linearity over process variation at multi-GHz rate of operation, which simplifies the calibration process. The time-to-digital converter was fabricated in a 0.13µm IBM CMOS process (CMRF8SF). At a sampling rate of 100MHz the maximum frequency of operation was measured to be 1.6GHz. The uncalibrated resolution of 8.1psec and a dynamic range of 260psec were measured. The TDC is compatible with loop counter architectures that can further extend its dynamic range. The raw integral (INL) and differential (DNL) non-linearity of 1.02LSB and 0.52LSB respectively were observed. A correlation with the simulated results confirmed that the proposed LPI-TDC can operate at 5GHz with some adjustments to measurement setup, input matching, and the on-chip supply integrity.