Floating-gate MOS transistors for Eraseable, Programmable, Read-only Memory (EPROM) application have been fabricated in V-groove Metal Oxide Semiconductor (VMOS) technology.
The operating characteristics of different configurations of transistors fabricated in the VMOS EPROM process have been analyzed. The purpose of this analysis was to determine a basis of comparison for devices fabricated in different ways, especially with regard to capacitive coupling to the floating gate, effects on threshold of drain and substrate (pi-layer) bias and breakdown conditions.
Previous methods of fabricating EPROMs and theories of charge injection were reviewed and related to the VMOS EPROM. Programmability was measured and analyzed in the light of the theories of charge injection. The importance of electron scattering in the image force potential well in the silicon dioxide was pointed out. Charge loss due to ultraviolet light erasure, intergate leakage, hole injection and long term temperature stress were measured and analyzed.