Pico-cell base-station power amplifiers (PA) generally generate less than 2W of power and operate at peak efficiency. This implies that to meet stringent wideband wireless standards, said amplifiers require linearization. The complexity and consequently power consumption of the linearizer is proportional to the power amplifiers efficiency and independent of output power. As a consequence, standard linearizers used in high PAs become unfeasible for use with pico-cell PAs as they are power intensive thus degrading the efficiency of the linearizer-PA combination. Feedback linearizers are only valid for narrowband stimuli while feedforward linearizers also suffer from the same total efficiency degradation due to the power consumption of the auxiliary amplifier. This leaves predistortion as the only viable option provided the algorithm/architecture is tailored to provide the same linearity benefit for high PAs as pico-cell PAs but with lower power consumption. The choice of neural networks as a predistortion algorithm compared to others such as Weiner, and Hammerstein stems from their ability to provide a suitable tradeoff between ACPR and EVM metrics. This thesis introduces an efficient dynamic neural network implementation which is specifically tailored for PA linearization. The focus and novelty of this work lies in the system inversion of measured PA non-linearity with a custom training algorithm as well as circuit design and hardware implementation of analog networks. Analog circuits are chosen to eliminate the power dependence of digital circuits on data rates; an effect which is most keenly felt for wideband stimuli. The implementation challenges include circuit design for large signal synaptic weights, wideband active delay elements, and an activation function. The aforementioned challenges have been tackled to yield a weight-limited algorithm which trains a neural network predistorter to improve the ACPR and EVM of the pico-cell power amplifier by at least 13.5dB and 8.7% respectively. Furthermore, the implemented analog neural network predistorter circuits have a bandwidth and linearity of 50MHz and 5 bits respectively with suggested improvements to increase the performance to 120MHz and 7 bits respectively.