Automated Pipelining for Clocked CMOS Logic and FPGAs
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Achieving multi-Gbps clock speeds with static CMOS logic requires migrating designs to smaller geometries, which present a higher development and fabrication cost. Instead, this research investigates the use of clocked CMOS logic to create an inherently pipelined circuit that can be clocked up to 2.5x faster than the standard cells available in the IC design kit. An algorithm was developed and implemented in Perl to process Verilog RTL netlists for compatibility with the clocked logic. As an example application, a cascaded integrator comb (CIC) filter for RF DSP was designed with the clocked CMOS and fabricated in the IBM 130 nm process. Unfortunately, due to an oversight with designing the boundary scan chain, true functionality of the circuit could not be verified. In another demonstration of concept, the algorithm was successfully applied to a QAM modulator design on a Xilinx Virtex-5 FPGA, which achieved a clock speed of 548 MHz.
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Copyright © 2016 the author(s). Theses may be used for non-commercial research, educational, or related academic purposes only. Such uses include personal study, research, scholarship, and teaching. Theses may only be shared by linking to Carleton University Institutional Repository and no part may be used without proper attribution to the author. No part may be used for commercial purposes directly or indirectly via a for-profit platform; no adaptation or derivative works are permitted without consent from the copyright owner.
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- 2016
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pepler-automatedpipeliningforclockedcmoslogicand.pdf | 2023-05-05 | Public | Download |