This thesis addresses the challenge of designing reliable and energy-efficient subthreshold flip-flops. A dual-clock-phase flip-flop (TG-FF) and a single-clock-phase flip-flop (SP-FF) configurations are considered and their gradual design modifications are reported towards perfecting their yields at minimum cost in terms of energy consumption. In addition, the two optimized flip-flop designs are compared in based on the criteria of static and dynamic energy consumptions, delay, and reliability in face of PVT variations.
A 65 nm and a newer 28 nm CMOS technology kit were used during the
course of this work. Multi-threshold MOSFETs and transistor sizing technique were incorporated for yield optimization. In general we were able to increase the flip-flops yields to 100% at the nominal temperature and power supply condition, and in the worst-case around 90% in the extreme cold and -10% noise on the power supply. We also prove the overall superiority of the SP-FF compared to TG-FF.