Design, Analysis and Modeling of the Effect of the Phase Detector in Digital Phase-Locked Loops

The limitations and the effect of the performance of the binary phase detector on the overall performance of the digital phase-locked loop is the main focus of the research presented in this proposal. In the first part of the research, the gain limitation of the binary phase detector on the performance of the digital Bang-Bang PLLs (BBPLL) is investigated. Then to validate the concept that is explained and to improve the performance of the digital loop under the gain limitation, two schemes are explored and explained. In one scheme a random bit-stream which is noise-shaped using a software defined ΣΔ modulator is used to dither the reference and improve the performance and in the second scheme a Time-Amplifier (TA) is used to improve the digital loop performance by preventing the phase detector from operating in metastable region.The second part of the research focuses on a novel multi-bit phase detector for high-speed applications where high-resolution performance is needed and the jitter budget is stringent. In this design a Transmission Delay Line (TDL) is used to generate the delayed versions of the input clock. The performance of this phase detector is analyzed in detail using stochastic analysis.In the second multi-bit, TDL based phase detector a search algorithm is used to find the closest delayed reference to the feedback clock. This scheme provides superior performance compared to the first scheme as its performance is not affected by the mismatch of the binary phase detectors used in the first scheme. The performance of the two design are compared and example of the performance in the loop is provided.