Domain-Specific Analog Accelerators for Artificial Intelligent Algorithms Implementation

This thesis discusses some circuit designs for AI algorithm acceleration. Instead of using digital computing components for algorithm implementations, this thesis describes new ideas to design and implement algorithms directly at the circuit-level. The first large section is about feedforward algorithm implementations that include using 1*4 analog multiply-accumulation arrays for DSP algorithm implementation and 2*3*3 analog multiply-accumulation matrices for computer vision algorithm and artificial intelligent algorithm implementations. The second large section concerns backward algorithm implementations that include using programmable resistor-based feedback loop, 'Add-division circuit' for convolutional kernel training algorithm implementation, and 'Random matrix generator' for solving Diophantine equations of neural networks.